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  We provide projects on wireless communication, WEKA, SentiWordNet, SDN, QUALlNet, OPNET, OpenCV, MiniNet, PEERSIM and so on

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  We do research on Wordnet, Grid Computing, Cloud Computing, Computer Networking, etc

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  We provide electrical projects based on power electronics, MATLAB Simulink and SIM Power

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  For Electronics Engineering Students we support technologies like ARM, GSM, GPS, RFID, Robotics, VLSI, NSL, NS3, OMNet++, OPNet, QUALNET, PeerSim

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  For Computer Science Students we support NS2, NS3, MATLAB, Java, OMNeT++, OPNet, CloudSim, Qualnet, Weka, Wordnet, Dot Net, Hadoop,….

Btech electrical engg projects

RELATED IEEE PROJECTS:

• Increased static RON in GaN-on-silicon power transistors under high-side operation with floating substrate conditions
• Extended configuration of dual active bridge DC–DC converter with reduced number of switches
• Design Optimization of Directly Grid-Connected PM Machines for Wind Energy Applications
• Electrowetting Displays Utilizing Bistable, Multi-Color Pixels Via Laser Processing
• An HDL-synthesized gated-edge-injection PLL with a current output DAC
• Very-large-scale integration implementation of a 16-bit clocked adiabatic logic logarithmic signal processor
• Variability-aware aging modeling for reliability analysis of an analog neural measurement system
• Digital VLSI Implementation of Piecewise-Affine Controllers Based on Lattice Approach
• Design of thin-film AlN actuators for 4-inch transparent plates for haptic applications
• Impulse response generation from S-parameters for power delivery network simulation
• A Low-Power VCO based ADC with asynchronous sigma-delta modulator in 65nm CMOS
• PFAL based power efficient mux based decoder
• Performance/energy trade-off in scientific computing: the case of ARM big.LITTLE and Intel Sandy Bridge
• A 1.3 mW low-IF, current-reuse, and current-bleeding RF front-end for the MICS band with sensitivity of -97 dbm
• Design of Full Adder Circuit Using Double Gate MOSFET
• Identification of high power consuming areas with gate type and logic level information
• A Pausible Bisynchronous FIFO for GALS Systems
• Read circuits for resistive memory (ReRAM) and memristor-based nonvolatile Logics
• 8% switching energy reduction in SAR ADC for bioelectronics application
• Payload power amplifier with average power tracking in Ka-band satellite downlink
• A digitally-controlled power-aware low-dropout regulator to reduce standby current drain in ultra-low-power MCU
• An All-Digital Delay-Locked Loop Using an In-Time Phase Maintenance Scheme for Low-Jitter Gigahertz Operations
• A novel energy-efficient data acquisition method for wearable devices
• HSTL based low power thermal aware adder design on 65nm FPGA
• 5 A 5.5mW 6b 5GS/S 4×-lnterleaved 3b/cycle SAR ADC in 65nm CMOS