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  We provide projects on wireless communication, WEKA, SentiWordNet, SDN, QUALlNet, OPNET, OpenCV, MiniNet, PEERSIM and so on

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  We do research on Wordnet, Grid Computing, Cloud Computing, Computer Networking, etc

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  We provide electrical projects based on power electronics, MATLAB Simulink and SIM Power

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  For Electronics Engineering Students we support technologies like ARM, GSM, GPS, RFID, Robotics, VLSI, NSL, NS3, OMNet++, OPNet, QUALNET, PeerSim

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  For Computer Science Students we support NS2, NS3, MATLAB, Java, OMNeT++, OPNet, CloudSim, Qualnet, Weka, Wordnet, Dot Net, Hadoop,….

M Tech VLSI Projects

VLSI PROJECTS LIST:

• Implementation of a high speed multiplier for high-performance and low power applications
• Joint Work and Voltage/Frequency Scaling for Quality-Optimized Dynamic Thermal Management
• Low power, high speed error tolerant multiplier using approximate adders
• Enhanced Wear-Rate Leveling for PRAM Lifetime Improvement Considering Process Variation
• New Methods for Simulation Speed-up and Test Qualification with Analog Fault Simulation
• C2-DLM: Cache coherence aware dual link mesh for on-chip interconnect
• Majority-Based Test Access Mechanism for Parallel Testing of Multiple Identical Cores
• Comparison of Off-Chip Training Methods for Neuromemristive Systems
• Design of Adiabatic Dynamic Differential Logic for DPA-Resistant Secure Integrated Circuits
• DScanPUF: A Delay-Based Physical Unclonable Function Built Into Scan Chain
• Fault modeling and testing of 1T1R memristor memories
• A 5.8-GHz Wideband TSPC Divide-by-16/17 Dual Modulus Prescaler
• Scaling the UVM_REG Model towards Automation and Simplicity of Use
• Wearout Resilience in NoCs Through an Aging Aware Adaptive Routing Algorithm
• Test vector omission with minimal sets of simulated faults
• Hardware Accelerator for Probabilistic Inference in 65-nm CMOS
• Bandwidth Adaptive Nanophotonic Crossbars with Clockwise/Counter-clockwise Optical Routing
• VANUCA: Enabling Near-Threshold Voltage Operation in Large-Capacity Cache
• Yield prognosis for fab-to-fab product migration
• A definition of the number of detections for faults with single tests in a compact scan-based test set
• No Fault Found: The root cause
• Economizing TSV Resources in 3-D Network-on-Chip Design
• Protein Alignment Systolic Array Throughput Optimization
• A Class of SEC-DED-DAEC Codes Derived From Orthogonal Latin Square Codes
• Write Buffer-Oriented Energy Reduction in the L1 Data Cache for Embedded Systems