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  We provide projects on wireless communication, WEKA, SentiWordNet, SDN, QUALlNet, OPNET, OpenCV, MiniNet, PEERSIM and so on

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  We do research on Wordnet, Grid Computing, Cloud Computing, Computer Networking, etc

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  We provide electrical projects based on power electronics, MATLAB Simulink and SIM Power

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  For Electronics Engineering Students we support technologies like ARM, GSM, GPS, RFID, Robotics, VLSI, NSL, NS3, OMNet++, OPNet, QUALNET, PeerSim

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  For Computer Science Students we support NS2, NS3, MATLAB, Java, OMNeT++, OPNet, CloudSim, Qualnet, Weka, Wordnet, Dot Net, Hadoop,….

Engineering Projects on VLSI

ENGINEERING PROJECTS ON VLSI:

• Embedded Tutorial ET1: Better-than-Worst-Case Timing Designs
• An efficient on-chip energy processing circuit for micro-scale energy harvesting systems
• High-Performance Deadlock-Free ID Assignment for Advanced Interconnect Protocols
• A 256-kb 9T Near-Threshold SRAM With 1k Cells per Bitline and Enhanced Write and Read Operations
• Thermal aware AND-OR-XOR network synthesis
• One-Cycle Correction of Timing Errors in Pipelines With Standard Clocked Elements
• Fabrication and characterization of Al gate n-MOSFET, on-chip fabricated with Si3N4 ISFET
• Fine-Grained Fast Field-Programmable Gate Array Scrubbing
• Accelerating Scalar Conversion for Koblitz Curve Cryptoprocessors on Hardware Platforms
• High Repair-Efficiency BISR Scheme for RAMs by Reusing Bitmap for Bit Redundancy
• A High-Speed FPGA Implementation of an RSD-Based ECC Processor
• Design for Testability of Sleep Convention Logic
• High-Speed, Low-Power, and Highly Reliable Frequency Multiplier for DLL-Based Clock Generator
• Scan Chain Masking for Diagnosis of Multiple Chain Failures in a Space Compaction Environment
• PNS-FCR: Flexible Charge Recycling Dynamic Circuit Technique for Low-Power Microprocessors
• Online Fault Tolerance Technique for TSV-Based 3-D-IC
• Two Phase Write Scheme to Improve Low Voltage Write-ability in Medium-Density SRAMs
• GenFin: Genetic Algorithm-Based Multiobjective Statistical Logic Circuit Optimization Using Incremental Statistical Analysis
• Analysis of CMOS inhibitory synapse with varying neurotransmitter concentration, reuptake time and spread delay
• Demystifying Iddq Data With Process Variation for Automatic Chip Classification
• σLBDR: Congestion-aware logic based distributed routing for 2D NoC
• An MPCN-Based BCH Codec Architecture With Arbitrary Error Correcting Capability
• A Wide-Range Multiport LC-Ladder Oscillator and Its Applications to a 1.2–10.1 GHz PLL
• A 3.6-mW 50-MHz PN Code Acquisition Filter via Statistical Error Compensation in 180-nm CMOS
• Standby leakage current estimation model for multi threshold CMOS inverter circuit in deep submicron technology

List of Projects