Scaling the UVM_REG Model towards Automation and Simplicity of Use

Scaling the UVM_REG Model towards Automation and Simplicity of Use The standard UVM register package contains built-in test sequences library which is used to perform most of the basic register and memory tests. These sequences are very useful at IP level verification but at SoC level verification where number of registers are very large, these sequences take very long time to run. Similarly, currently users require strong knowledge of SV UVM language to use UVM_REG register model and verification environment code seems to be very complex to verification engineers/designers which are not expert in UVM. Some limitations in current version of UVM_REG package like no automatic data checking for memory accesses and limited support for memory burst operation were also seen. In this paper, we are describing how we addressed the above mentioned issues. We are accessing processor programmable registers and memories through a standard API (based on UVM_REG register model) used in test development. This API is aimed at writing simpler directed tests which require less or no SV/UVM understanding. This API can be used to facilitate dumping register access for reuse from IP to SoC, or format outputs for use in ATE test vectors development etc. In these APIs, basic to more complex OS based capability is provided. We also developed our own register/memory sequences to address the SoC level register and memory testing. Customized code is written to enhance the features of standard UVM_REG Register and Memory Model. IP-XACT based tools are also developed to automatically generate all required verification environment files for using standard register model. Verification Environments with UVM_REG register model integrated are used to verify a variety of devices covering various protocols, applications and domains as the Internet of Things (IoT).