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Adjacent-MBU-Tolerant SEC-DED-TAEC-yAED Codes for Embedded SRAMs

Adjacent-MBU-Tolerant SEC-DED-TAEC-yAED Codes for Embedded SRAMsAs technology scaling increases embedded static random access memory bit-cell density, the number of soft errors due to radiation-induced multiple-bit upsets (MBUs) also increases. Traditionally, these errors have been addressed using a simple error correction code (ECC) combined with word interleaving. With continued scaling, however, errors beyond this setup begin to emerge. Although more powerful ECCs exist, they come at an increased overhead in terms of area and latency. Additionally, interleaving adds complexity to the system and may not always be feasible for the given architecture. In this brief, a set of double adjacent error correction (DAEC) codes is modified to provide triple adjacent error correction for a cost of zero additional check-bits over the code’s DAEC equivalent, yielding a 2.25× reduction in bit-level soft error rate for a 22-nm MBU error channel model. MATLAB simulation and HDL synthesis results are included for standard 16- and 32-data-bit memory word sizes and compared against existing codes.

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