Thermal aware AND-OR-XOR network synthesis

Thermal aware AND-OR-XOR network synthesis An essential job of combinational logic synthesis is to optimize the area and power of the synthesized circuit. Two-level and three level logic minimization for area and power are the well researched areas. Recently temperature minimization has been emerged as the new dimension in logic synthesis. Thermal aware AND-OR-XOR network realization is considered in this research work. In this paper attention has also been drawn towards multilevel realization of the corresponding AND-OR-XOR circuit to get a final circuit that is optimized in terms of area as well as power density. Power density is the measure of temperature, so, this work targets the thermal aware multi level synthesis by optimizing power density. The optimization algorithm used here is Genetic algorithm. The final optimized circuit is then simulated in Cadence Encounter and HotSpot tool to get the absolute temperature.