Circuit Level Defences Against Fault Attacks in Pipelined NCL Circuits

Circuit Level Defences Against Fault Attacks in Pipelined NCL Circuits As a type of side-channel attack, fault attacks on the hardware implementation of cryptographic algorithms has been widely studied, and has been successfully applied to a variety of ciphers. So far, many hardware countermeasures against fault attacks have been proposed. However, most of them are tailored to a specific cryptographic algorithm and cannot provide a comprehensive level of protection against all possible faults. In this paper, we present a novel, secure and generic framework based on the robustness of null convention logic pipelines and dual-rail encoded systems, which is resistant to fault attacks at the circuit level by implementing technologies such as rail synchronization, maximum delay matching, error-detecting monitors, and self-feedback mechanisms. Both the theoretical analysis and simulation results show that all faults at the output of computational blocks can be fully detected and corrected. The new framework gives us the ability to detect and correct the faults induced in the register.