An HDL-synthesized gated-edge-injection PLL with a current output DAC

An HDL-synthesized gated-edge-injection PLL with a current output DAC This paper presents a small area, low power, fully synthesizable PLL with a current output DAC and an interpolative-phase coupled oscillator using edge injection technique for on-chip clock generation. A prototype PLL is fabricated in a 65nm digital CMOS process, achieves a 1.7-ps integrated jitter at 0.9 GHz and consumes 0.78 mW leading to an FOM of -236.5 dB while only occupying an area of 0.0066 mm². It achieves the best performance-area trade-off.