A digitally-controlled power-aware low-dropout regulator to reduce standby current drain in ultra-low-power MCU

A digitally-controlled power-aware low-dropout regulator to reduce standby current drain in ultra-low-power MCU In this paper, we describe a fully-integrated digitally-controlled low-dropout regulator (LDO) with dual-loop architecture, providing core voltage to an ultra-low-power microcontroller (MCU). The fine-grained loop dynamically modulates the active-mode LDO drive-strength using the MCU power-modes information for a maximum load current of 6mA, thereby improving the active-mode current efficiency. The coarse-grained loop, enabled to regulate the output voltage only when the MCU enters the standby-mode, ensures ultra-low quiescent current consumption of 500nA, preventing standby drain. A thermometric binary-weighted power-switch matrix improves the transient response figure-of-merit (FOM) by switching between the different power modes. A charge-pump based voltage monitoring circuit is added to allow for wider input voltage range with reduced ripple. Fast digitally-controlled transient response of the LDO allowed the replacement of the (usually off-chip) large capacitor with a high-density on-chip ferroelectric capacitor, thus reducing the LDO sleep-to-active recovery time/energy and allowing full system-on-chip integration. The digitally-controlled LDO, with a wide input voltage range of 1.75-3.3V and nominal output of 1.2V is implemented in a 0.13μm CMOS technology with an active area of 0.034mm², achieving a FOM of 4.44ps with standby-mode current efficiency of more than 90% for all practical purposes.