HSTL based low power thermal aware adder design on 65nm FPGA

HSTL based low power thermal aware adder design on 65nm FPGA In this paper an approach is made to design most power and energy efficient Full Adder and for that reason we have used four different members of HIGH SPEED TRANSCEIVER LOGIC (HSTL) IO Standard family. In this design, we have taken two main parameters for analysis that are Heat Sink and Air Flow. We have taken one value for LFM i.e. 250 and Medium as a default profile for heat sink. For the simulation of the logic, Xilinx is used with Verilog as hardware description language. When we scale down ambient temperature from 343.15K to 283.15K, then there is reduction in leakage power, Maximum Ambient Temperature and junction temperature of the order of 17.12% to 49.38%, 0.23% to 0.71%, and 21.34% to 84.97% respectively. There is also a reduction in IO power of order of 39.53%, 15.50%, and 8.52% with the change in HSTL family.