Design and implementation of time to digital converters

Design and implementation of time to digital converters Modern VLSI technology is mainly driven by digital circuits because digital circuits has many advantages over analog circuits. By using very small and simple circuits atomic digital functions can be realized. All digital phase locked loops (ADPLL) plays an important role in applications such as Bluetooth, GSM and Wi-Fi. A Time to digital converter (TDC) is the critical part in the ADPLL. The concept of TDC is to sample the outputs of all delay elements at the same time. To know the performance of TDC we are analyzing various TDC architectures using buffers and inverters. Flash type TDC have less resolution which uses single delay line. Whereas Vernier delay line TDC uses two delay lines which resolves finely. Replica delay line TDC reduces mismatches among the delay cells. The Vernier ring TDC places the Vernier delay cells in a ring format and reuses them for the measurement of the input time interval. This TDC architecture will give high resolution than conventional TDC models. The power consumed by various TDC architectures are analyzed. Analysis are done by using Xilinx and cadence virtuoso gpdk 180nm technology.