A 10 Gbps eye opening monitor in 65nm CMOS

A 10 Gbps eye opening monitor in 65nm CMOS Monitoring the eye diagram at the output of an embedded analog adaptive equalizer used in a high speed serial link is challenging. Eye measurement using an external oscilloscope is problematic due to the bandwidth of the test setup. In this work, we describe the working principle and design details of a low cost, on-chip monitor circuit that enables the determination of the eye diagram. The eye opening monitor (EOM), implemented in a 65 nm CMOS process, occupies 0.06 mm² and consumes 5.7 mW from a 1.2 V supply. Measurements demonstrate the efficacy of our techniques.