26.7 A 2.6b/cycle-architecture-based 10b 1 JGS/s 15.4mW 4×-time-interleaved SAR ADC with a multistep hardware-retirement technique

26.7 A 2.6b/cycle-architecture-based 10b 1 JGS/s 15.4mW 4×-time-interleaved SAR ADC with a multistep hardware-retirement technique With the growing interest in time-interleaved (TI) structures, the conversion rates of ADCs have greatly improved, which has inevitably increased power consumption. Despite the advantages of TI structures,power consumption is increased due to the stricter matching requirements between channels; in some cases, >50% of total power is for calibration purposes. Thus, to realize high-speed and high-resolution ADCs with TI structures, it is important to alleviate the calibration burden by choosing a suitable number of power-efficient high-speed single channels. Previously reported CDAC-based 2b/cycle structures made contributions in realizing high-speed single-channel ADCs with high resolution by using additional capacitive DACs and modified switching logic. The power overhead and the complexity of the additional logic and DACs for 2b/cycle implementations have been of trivial concern for low resolution ADCs. However, as resolution increases, the complexity of such circuits becomes considerable, with powertaking up a big share of the total. In this paper, a multi-step hardware-retirement (MSHR) technique, which disables low-accuracy hardware blocks of scaled sizes with the requirement relaxations from redundancies in an advancement to the reconfiguration scheme in the work of Kong et al. (2013), is reported to alleviate the overhead of additional logic and DACs for ADCs, requiring high resolutions. A low-power 2.6b/cycle-based SAR ADC architecture is presented as a proof of concept.