17.3 A 28nm 256kb 6T-SRAM with 280mV improvement in VMIN using a dual-split-control assist scheme

17.3 A 28nm 256kb 6T-SRAM with 280mV improvement in VMIN using a dual-split-control assist scheme Intelligent wearable devices and the Internet of things (IoT) require on-chip SRAM macros with (1) compact area to reduce costs; (2) single supply voltage (VDD) and low minimum VDD (VDDmin) to reduce power consumption; and (3) sufficient speed to facilitate real-time computing. 6T SRAM is compact, but suffers write failure and half-select (HS) disturbance in read/write cycles at low VDD. Previous studies have sought to improve the write margin (WM)of SRAMs by (a) lowering the cell-VDD (CVDD) voltage (=VDD-ΔV_cVVD) [1]-[3] (CVDD-D) at the expense of degradation in cell stability (static noise margin, SNM) for CVDD-HS cells; or (b) using negative-bitline (NBL) voltage (=VSS-V_NBL) [1,4-6] for cross-point assist at the expense of increased area and power overhead due to the inclusion of pumping capacitors (C_NBL). Wordline (WL) voltage under-drive (WLUD, V_WL=VDD-V_WLUD) is commonly used in 6T SRAMs [2-5] to improve HS/read SNM during read/write cycles; however, this tends to degrade WM and cell read current (I_CELL), resulting in slower read/cycle speeds and necessitating an increase in ΔV_CVDD or V_NBL (C_NBL). The maximum ΔV_CVDD is limited by the hold SNM of CVDD-HS cells. Large C_NBL results in large area and power overhead, particularly in macros with wide I/O and small amount of column-multiplexing (Y-mux). Thus, HS-SNM tradeoffs in l_CELL and WM have not yet been solved for 6T cells, except by adding additional transistors (i.e., 8T to 10T).