8.3 A 10.5μA/MHz at 16MHz single-cycle non-volatile memory access microcontroller with full state retention at 108nA in a 90nm process

8.3 A 10.5μA/MHz at 16MHz single-cycle non-volatile memory access microcontroller with full state retention at 108nA in a 90nm process With the Internet of Things (IoT) becoming ubiquitous, there is an ever-increasing demand for loweringpower dissipation, especially for sensor nodes, where low energy consumption translates to longer battery life or operation with a smaller/cheaper battery. At the heart of a sensor node is a microcontroller running code from an embedded non-volatile memory (NVM). In order to support increasing computational needs and low latency (the ability to respond quickly to an event), the microcontroller needs to run at high performance (8-16MHz) and still have low power dissipation. Since most of sensor-node applications are event driven, the nodes, when not active, go into standby mode, to reducepower dissipation. In order to minimize the total energy consumption, it is important to not only reduce active-mode power, but to also lower the power consumption in standby mode, and have the ability to switch between the modes with low latency and low transition energy. Multiple low-powermicrocontroller implementations have been discussed in literature. Some, such as [1,2,3], aggressively address active mode power, but have higher standby mode power and also do not support CPU state retention. Other approaches [4,5], aggressively address the standby mode power, but have higher active-mode power, especially for code running from non-volatile memory. In this paper, we present an ultra-low-power microcontroller which addresses both active as well as standby-mode power reduction, and hence results in significantly lower total energy over a wide range of active-mode to standby-mode ratios (“duty cycle”).