A DfT Architecture and Tool Flow for 3-D SICs With Test Data Compression, Embedded Cores, and Multiple Towers

A DfT Architecture and Tool Flow for 3-D SICs With Test Data Compression, Embedded Cores, and Multiple Towers This paper proposes a design-for-test architecture for efficient testing of 3-D ICs. The DfT architecture supports multiple dies, test data compression, and embedded cores. Commercial EDA tools are used to implement the DfT architecture.