A Novel Failure Diagnosis Approach for Low Pin Count and Low Power Compression Architectures

A Novel Failure Diagnosis Approach for Low Pin Count and Low Power Compression Architectures This paper presents a novel approach for performing diagnosis in test access mechanisms (TAM) architectures based on time domain multiplexing and serial scan shifting. These TAM architectures allow efficient application of low power compressed patterns to individual embedded cores present in SoCs using limited pins. The proposed diagnosis approach relies on the connectivity information of the TAM architecture to map SoC level failures to a particular embedded core. These TAM architectures allow high level of diagnosis resolution and performance.