Design and implementation of field programmable gate array based error tolerant adder for image processing application

Design and implementation of field programmable gate array based error tolerant adder for image processing application In the era of low power, high performance digital systems are needed to boost up the technology revolution in nano-electronics. Realization of new digital logic is essential for making revolutionary changes in low power and high speed performance. In modern VLSI technology, the occurrence of all kinds of errors has become inevitable. By adopting an emerging concept in VLSI design and test, error tolerance (ET), a novel error-tolerant adder (ETA) is proposed. The ETA is able to ease the strict restriction on accuracy, and at the same time achieve tremendous improvements in both the power consumption and speed performance. A robust and efficient error-tolerant adder (ETA) is proposed in this project and it is compared with its conventional counterparts, with respect to power consumption and high speed. The proposed ETA is then applied for an image processing application and tested for its performance in terms of error tolerance. A novel type of adder, the error-tolerant adder, which trades certain amount of accuracy for significant power saving and performance improvement, is proposed. One example of such applications is in the image processing.