Digital on-chip measurement circuit for built-in phase noise testing

Digital on-chip measurement circuit for built-in phase noise testing This paper presents a digital on-chip measurement circuit for built-in phase noise evaluation of analog/IF signals. The technique relies on 1-bit acquisition and on-the-fly processing to compute a digital signature related to the phase noise level present in the analog signal. In order to minimize the required hardware resources, the circuit is designed with a semipipeline architecture and modular arithmetic. It has been implemented for validation on a FPGA-based platform. Experimental measurements on both a synthesized signal and the IF output of a silicon tuner demonstrate a very good agreement with the conventional external technique.