High Repair-Efficiency BISR Scheme for RAMs by Reusing Bitmap for Bit Redundancy

High Repair-Efficiency BISR Scheme for RAMs by Reusing Bitmap for Bit Redundancy A built-in self-repair (BISR) scheme for random access memories (RAMs) with 2-D redundancy has a built-in redundancy analyzer (BIRA) for allocating the redundancy. The BIRA typically has a cache-like element called local bitmap for storing the fault information temporary. In this paper, a high-repair-efficiency BISR (HRE-BISR) scheme for RAMs is proposed. The HRE-BISR reuses the local bitmap to serve as spare bits such that it can repair more faults. In addition, a row/column/bit redundancy analysis (RCB-RA) algorithm for a RAM with spare rows, spare columns, and spare bits is presented. Simulation results show that the proposed HRE-BISR scheme can provide higher repair rate (RR) than a typical BISR scheme without reusing the local bitmap as spare bits. Only about 0.44% additional hardware overhead is needed to modify the local bitmap as spare bits. In addition, the HRE-BISR scheme using $3times 3$ -bit local bitmap for RA only incurs about 0.08-ns delay penalty for a$512times 16times 32$ -bit RAM with one spare row and one spare column. However, the HRE-BIRA scheme with RCB-RA algorithm can provide 0.48%–11.95% increment of RR for different fault distributions.