Low power, high speed error tolerant multiplier using approximate adders

Low power, high speed error tolerant multiplier using approximate adders In most of the multimedia applications such as audio, speech, graphics and video the final output is interpreted by human senses, which are insensitive to small errors. So, it is not required to produce exact numerical outputs. Considering the advantage of relaxation in numerical accuracy, this paper propose several approximate multipliers for error tolerant applications which are designed by using approximate adders. Approximate adder is constructed by reducing the complexity at the transistor level. The power consumption is reduced due to decrease in number of transistors and switched capacitance. Decrease in the number of series connected transistors, lead to shorter critical paths. Propagation delay is appreciably reduced due to decrease in load capacitance. The operation of 4×4, 8×8 and 16×16 approximate array multipliers are discussed in this paper. Simulation results show that for random inputs, upto 64% savings in power delay product is achieved using the proposed multiplier, when compared with the conventional multiplier.