Low voltage LNA implementations in 28 nm FD-SOI technology for GNSS applications

Low voltage LNA implementations in 28 nm FD-SOI technology for GNSS applications In this paper a comparison of four low noise amplifiers (LNAs), designed in fully depleted SOI 28 nm technology, has been presented. The objective of the presented work was to verify the usability of all kinds of MOSFET transistors that are available in UTBB for RF analog designs. The inductively degenerated cascodes were used in simulations. Such topology achieves high gain and low noise figure (NF). Simulated amplifiers were designed for a high sensitivity GNSS receiver, which operates in the Galileo/GPS E1/L1 band. The implemented circuits demonstrate the gain of 22.3 dB and the consumption current of 2.5 mA, with NF equal to 1.92 dB. For all amplifiers the supply voltage is 0.6 V and the silicon die estimated area is equal to 0.7 mm².