Sub-50nm monolithic 3D IC with low-power CMOS inverter and 6T SRAM

Sub-50nm monolithic 3D IC with low-power CMOS inverter and 6T SRAM For the first time, a sequentially processed was demonstrated using low thermal budget processed ultrathin-body (UTB) channel technique. High-performance sub-50nm high-k/metal gate UTB MOSFETs using super-CMP-planarized laser crystallized epi-like Si ultra-thin channel (15nm) enable stackable 6T SRAMs with static noise margin (SNM) of 390 mV at operation voltage of 1V and reduced footprint by 25%. Closely stacked monolithic 3D circuits envision advanced high-performance, rich function, and low power intelligent mobile devices.