Test vector omission with minimal sets of simulated faults

Test vector omission with minimal sets of simulated faults Test vector omission is a static test compaction procedure for functional test sequences that removes unnecessary test vectors from a sequence. The test vector omission procedure requires fault simulation for every test vector (or subsequence) that it considers for omission. It was noted earlier that it is possible to reduce the set of simulated faults based on the clock cycles where the faults are detected. However, this reduction is effective only for the later test vectors of a sequence. This paper defines a minimal set of faults that need to be simulated for the omission of a test vector by considering, in addition to detection clock cycles, also clock cycles where test subsequences start. The former are computed by a conventional sequential fault simulation process. For the latter, the paper introduces a sequential reverse order fault simulation process, and an approximation with a reduced computational complexity. Experimental results show significant reductions in the run time for test vector omission without affecting the level of compaction.